这项工作得到了日本文部科学省（MEXT）的日本科学促进会（JSPS）KAKENHI（17J10044）的资助。制造工艺得到了日本文部科学省"纳米技术平台"（项目编号12024046）的支持。作者要感谢东京大学的K. Yamashita先生和平田S. Ms. Hirata女士在TEM观测方面的帮助。

1. 理论计算程序
<ol><li>计算TD的轨迹。在计算中，假设 SEG 掩码足够薄，可以忽略 ART 对 TDD 减少的影响。<ol><li>确定生长表面并用方程表示。例如，使用时间演化参数 n = i、SEG Ge 高度 （h i） 和 SEG Ge 半径 （r i） 表示 SEG Ge 层圆形横截面的时间演变，如补充视频 1a 和等式 （1） 所示: <img alt="Equation 4" src="/files/ftp_upload/58897/58897eq4.jpg" style="opacity: 0.9;"></li>
		<li>确定生长表面上任意位置的法线方向。对于圆形截面SEG Ge，将（x i，yi）处的法线描述为，如<img alt="Equation 7" src="/files/ftp_upload/58897/58897eq7v2.jpg" style="opacity: 0.9;">补充视频1b所示为红线。然后，通过求解以下联立方程组，从点（x i ， y i）获得TD（x i + 1，yi + 1）的边: <img alt="Equation 10" src="/files/ftp_upload/58897/58897eq10.jpg" style="opacity: 0.9;"></li>
		<li>根据TD生成的位置（x 0，0）计算一个TD的轨迹，如补充视频1c所示。换句话说，可以通过上述方法计算任意TD的轨迹。</li>
		<li>假设TD穿透底面并有助于TDD的减少（即，低于SEG Ge层聚结点的TD被半圆柱形空隙捕获并且永远不会出现在顶面）计算TDD。</li>
	</ol></li>
</ol>2. 实验验证程序
<ol><li>赛格面罩准备<ol><li>在制造 SEG 掩模之前，通过准备设计文件来定义 Ge 生长区域。在本工作中，使用商业软件（例如AutoCAD）准备与[110]方向对齐的线和空间图案以及宽度为4毫米的方形Si窗口区域。</li>
		<li>使用软件确定SEG掩模（特别是W窗口和W掩模）的设计。W 窗口是窗口宽度（Si 种子宽度），W 掩模是 SiO2 掩模宽度，使得 SEG Ge 层可以与其相邻层合并。通过单击打开的文件→结构→矩形或多段线来绘制矩形来确定 W窗口和 W蒙版。 注意: 矩形的宽度变为 W窗口，矩形的间隔变为 W掩码。在本工作中，W窗口 和W掩模 的最小值分别为0.5 μm和0.3 μm，这受到所采用的EB光刻系统中分辨率的限制。</li>
		<li>作为参考，绘制宽度为 D 的 4 mm 的方形 Si 窗口区域，视为毯子区域。单击" 打开文件"→结构→矩形或折线 以绘制方形 Si 窗口。使用 图1 所示的原理图准备线和空间图案以及4 mm方形毯区域。</li>
		<li>制备电阻率为1-100 Ω∙cm的B掺杂p-Si（001）衬底。在本工作中，使用4英寸Si基板。必要时用食人鱼溶液（20 mL 30% H 2 O 2 和 80 mL 96% H2SO4 的混合物）清洁基材表面。</li>
		<li>打开管式炉的盖子，使用玻璃棒将硅基板装入炉中。在本工作中，一次氧化10个Si基底。</li>
		<li>通过打开气阀开始将干燥的N2 气体吹入炉中。然后，通过控制阀门将气体流量设置为 0.5 L/m。</li>
		<li>通过更改程序设置退火温度。在本工作中，使用"图案步骤（模式2）"并将工艺温度设置为900°C。 然后，通过推送 函数运行→程序。</li>
		<li>当温度达到900°C时，关闭干燥的N2阀，打开干燥的O 2阀（O 2流量= 1L / m），并保持2小时。 注意:在黄色房间中执行步骤 2.1.9-2.1.16。</li>
		<li>使用旋涂机用表面活性剂（OAP）涂覆氧化的Si基底，然后在110°C下在加热板上烘烤90秒。</li>
		<li>表面活性剂涂覆后，使用旋涂机用光刻胶（例如ZEP520A）涂覆Si基底，然后在180°C下在加热板上烘烤5分钟。</li>
		<li>将表面活性剂和光刻胶装入Si基底到电子束（EB）刻录机中。</li>
		<li>在EB编写器中读取设计文件（在步骤2.1.2中准备）并制作操作文件（WEC文件）。在WEC文件中将剂量设置为120μC / cm2 。基板加载完成后，通过单击单个曝光按钮进行EB 曝光 。</li>
		<li>通过单击 晶圆进位 从EB写入器卸载基板→在曝光结束时卸载。</li>
		<li>在通风室中准备光刻胶显影剂（ZED）和冲洗剂（ZMD）。将暴露的Si基底在室温下浸入显影剂中60秒。</li>
		<li>从显影剂上去除Si基底，然后用N2 气体干燥基板。</li>
		<li>将显好的Si基板放在加热板上，在110°C下烘烤90秒。</li>
		<li>将Si基底浸入缓冲氢氟酸（BHF-63SE）中1分钟，以去除由于EB暴露和发育而暴露在空气中的部分SiO2 层。</li>
		<li>通过浸入有机光刻胶去除剂（例如Hakuri-104）中15分钟，从Si衬底上去除光刻胶。</li>
		<li>将Si衬底浸入0.5%稀释的氢氟酸中4分钟，以去除窗口区域中的稀天然氧化物，但保留SiO2 掩膜。然后加载到超高真空化学气相沉积（UHV-CVD）室中以生长Ge。 图2 显示了本工作中使用的UHV-CVD系统。</li>
	</ol></li>
	<li>外延锗生长<ol><li>将带有SEG掩模的Si衬底（如步骤2.1中制造）装入负载锁定室。</li>
		<li>在操作计算机上显示的 配方 选项卡中设置缓冲液/主生长温度。确定Ge主要生长的持续时间，以便SEG Ge层与相邻层合并。要确定主要增长的持续时间，请考虑 Ge 在{113}平面上的增长率，它决定了面内/横向方向的增长26。在本工作中，将650°C和700°C的主要生长持续时间分别设置为270分钟和150分钟。</li>
		<li>在主窗口中单击 开始 ，然后将Si衬底自动转移到生长室中。 注意:外延锗生长方案（步骤2.2.4-2.2.7）将自动处理。</li>
		<li>在低温（≈380°C）下在负载的Si衬底上生长Ge缓冲液。使用在Ar中稀释9%的GeH 4作为源气，并在缓冲液生长期间将GeH4的分压保持在0.5 Pa。</li>
		<li>在高温下生长Ge主层。在主要生长期间将GeH4 的分压保持在0.8 Pa。在本工作中，使用650和700 °C两种不同的温度作为主要生长温度，以便将SEG Ge与圆形截面和{113}面截面25进行比较。 注意:（001）平面上Ge的生长速率为11.7nm/min，与温度无关。</li>
		<li>为了可视化SEG Ge的演变及其聚结，通过在另一个Si衬底上定期插入10nm厚的Si 0.3 Ge0.7分界层来进行Ge生长。Si0.3 Ge 0.7层是使用Si2H6和GeH 4气体形成的。在Si 0.3 Ge 0.7层生长过程中，将Si2H6气体的分压设置为0.02 Pa，将GeH4气体的分压设置为0.8Pa。</li>
		<li>当Si衬底自动从生长室转移到负载锁定室时，请排放负载锁定室并手动卸载Si衬底。</li>
	</ol></li>
	<li>蚀刻坑密度 （EPD） 测量<ol><li>使用超声波清洗机将 32 mg I2 溶解在 67 mL 的 CH3COOH 中。</li>
		<li>混合I2溶解的CH 3 COOH，20 mL HNO3和10 mLHF。</li>
		<li>将锗生长的硅基底浸入CH 3 COOH/ HNO3/ HF/ I 2溶液中5-7秒，以形成蚀刻凹坑。</li>
		<li>用光学显微镜（通常为100倍）观察蚀刻的Ge表面，以确保蚀刻的凹坑成功形成。</li>
		<li>使用原子力显微镜（AFM）来计数蚀刻的凹坑。将蚀刻的Ge样品放在AFM载物台上，然后单击自动接近 接近探针。</li>
		<li>使用与AFM集成的光学显微镜确定观察区域，并扫描五个不同的10 μm x 10 μm区域。幅度阻尼因子是自动确定的。</li>
	</ol></li>
	<li>透射电镜观测<ol><li>使用聚焦的Ge离子束（FIB微采样方法）从聚结/毯状Ge层中拾取TEM样品27。</li>
		<li>使用氩离子在离子研磨系统中抛光TEM试样。在本工作中，用于横截面观测的TEM试样在[110]方向上为150-500 nm，在[001]方向上将平面视图观测的透视图样品减薄为200 nm。</li>
		<li>对于平面透射电镜试样，用非晶层保护Ge层的顶面，然后从Ge层的底部（基底）侧向下变薄。</li>
		<li>在 200 kV 的加速电压下进行 TEM 观察。执行横截面明场扫描透射电镜 （STEM） 观察，以观察厚 （500 nm） 透射电镜标本。</li>
		<li>对于具有Si0.3 Ge 0.7分界层的聚结Ge，在200 kV的加速电压下进行横截面高角度环形暗场（HAADF）STEM观测。</li>
	</ol></li>
</ol>

作者没有什么可透露的。

在本工作中，实验显示了4 x 107 / cm2 的TDD。为了进一步降低TDD，协议中主要有2个关键步骤:SEG掩膜制备和外延Ge生长。
图4所示的模型表明，当APR，W窗口/（W窗口+ W掩模）小至0.1时，TDD可以降低到107 / cm2在聚结Ge中。为了进一步降低TDD，应准备具有较小APR的SEG口罩。如步骤2.1.2所述，W窗口和W...

Si上的外延锗作为有源光子器件平台引起了广泛兴趣，因为Ge可以检测/发射光通信范围（1.3-1.6μm）内的光，并且与Si CMOS（互补金属氧化物半导体）加工技术兼容。然而，由于Ge和Si之间的晶格失配高达4.2%，因此在Si上的Ge外延层中以~109 / cm2的密度形成螺纹位错（TDs）。由于TD在Ge光电探测器（PD）和调制器（MOD）中充当载流子生成中心，在激光二极管（LDs）中充当载流子复合中心，因此锗光子器件的性能会因TD而恶化。反过来，它们会增加PD和MOD1，2，3中的反向泄漏电流（J泄漏）和LDs4，5，6中的阈值电流（J th）。
据报道，已经有各种尝试来降低Si上Ge中的TD密度（TDD）（补充图1）。热退火刺激TD的运动，导致TDD降低，通常为2 x 107 / cm2。缺点是Si和Ge可能混合，并且掺杂剂在Ge中扩散，例如磷7，8，9（补充图1a）。SiGe分级缓冲层10，11，12增加了临界厚度并抑制了TD的产生，导致TDD降低，通常为2 x 106/cm2。这里的缺点是厚缓冲器会降低Ge器件和下方Si波导之间的光耦合效率（补充图1b）。纵横比捕获 （ART）13，14，15 是一种选择性外延生长 （SEG） 方法，通过将 TD 捕获在厚 SiO 2 沟槽的侧壁上来降低 TD，通常为 <1 x 10 6/cm 2。ART方法使用较厚的SiO 2掩模来降低Ge中的TDD，而不是SiO 2掩模，SiO2掩模远高于Si，并且具有相同的缺点（补充图1b，1c）。Si柱晶种上的Ge生长和退火16，17，18与ART方法相似，通过高纵横比Ge生长使TD捕获达到<1 x 105/cm2。然而，用于Ge聚结的高温退火在补充图1a-c（补充图1d）中具有相同的缺点。
为了在硅上实现低TDD的Ge外延生长，而不受上述方法的缺点，我们根据迄今为止在SEG Ge生长7，15，21，22，23中报告的以下两个关键观察结果，提出了聚结诱导的TDD还原19，20:1）TD弯曲成垂直于生长表面（通过横截面透射电子显微镜（TEM）观察），2）SEG Ge层的聚结导致在SiO2掩模上形成半圆柱形空隙。
我们假设TD由于生长表面的成像力而弯曲。在Si上的Ge的情况下，像像力分别在距离自由表面1 nm处产生1.38 GPa和1.86 GPa的螺杆位错和边缘位错的剪切应力19。计算出的剪切应力明显大于Ge24中报告的60°位错的Peierls应力0.5 GPa。该计算预测了Ge SEG层的TDD减少，并且与SEG Ge增长19非常吻合。对TD进行TEM观察以了解Si20上所呈现的SEG Ge生长中的TD行为。镜像力诱导的TDD还原没有任何热退火或厚缓冲层，因此更适合光子器件应用。
本文介绍了TDD还原方法的理论计算和实验验证的具体方法。

<table><tbody><tr><td>AFM</td><td>SII NanoTechnology</td><td>SPI-3800N</td><td></td></tr><tr><td>BHF</td><td>DAIKIN</td><td>BHF-63U</td><td></td></tr><tr><td>CAD design</td><td>AUTODESK</td><td>AutoCAD 2013</td><td>Software</td></tr><tr><td>CH&lt;sub&gt;3&lt;/sub&gt;COOH</td><td>Kanto-Kagaku</td><td>Acetic Acid</td><td>for Electronics</td></tr><tr><td>CVD</td><td>Canon ANELVA</td><td>I-2100 SRE</td><td></td></tr><tr><td>Developer</td><td>ZEON</td><td>ZED</td><td></td></tr><tr><td>Developer rinse</td><td>ZEON</td><td>ZMD</td><td></td></tr><tr><td>EB writer</td><td>ADVANTEST</td><td>F5112+VD01</td><td></td></tr><tr><td>Furnace</td><td>Koyo Thermo System</td><td>KTF-050N-PA</td><td></td></tr><tr><td>HF, 0.5 %</td><td>Kanto-Kagaku</td><td>0.5 % HF</td><td></td></tr><tr><td>HF, 50 %</td><td>Kanto-Kagaku</td><td>50 % HF</td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt;, 61 %</td><td>Kanto-Kagaku</td><td>HNO3 1.38</td><td>for Electronics</td></tr><tr><td>I&lt;sub&gt;2&lt;/sub&gt;</td><td>Kanto-Kagaku</td><td>Iodine 100g</td><td></td></tr><tr><td>Photoresist</td><td>ZEON</td><td>ZEP520A</td><td></td></tr><tr><td>Photoresist remover</td><td>Tokyo Ohka</td><td>Hakuri-104</td><td></td></tr><tr><td>Surfactant</td><td>Tokyo Ohka</td><td>OAP</td><td></td></tr><tr><td>TEM</td><td>JEOL</td><td>JEM-2010HC</td><td></td></tr></tbody></table>

theoretical calculation and experimental verification for dislocation reduction in germanium epitaxial layers with semicylindrical voids on silicon

降低硅（Si）上外延锗（Ge）的螺纹位错密度（TDD）是实现单片集成光子电路的最重要挑战之一。本文介绍了一种降低TDD的新模型的理论计算和实验验证方法。理论计算方法描述了基于TDs与选择性外延生长（SEG）的非平面生长表面在位错成像力方面的相互作用的螺纹位错（TDs）的弯曲。计算表明，SiO2 掩模上空隙的存在有助于降低TDD。采用超高真空化学气相沉积法和TD观察生长的锗（Ge）SEG通过蚀刻和横截面透射电子显微镜（TEM）对生长的Ge进行实验验证。强烈建议TDD降低是由于SiO2 SEG掩模和生长温度上存在半圆柱形空隙。为了进行实验验证，由于Ge层的SEG及其聚结作用，形成了具有半圆柱形空隙的外延Ge层。实验得到的TDDs基于理论模型再现了计算出的TDD。横断面透射电镜观察表明，TD的终止和生成都发生在半圆柱形空隙处。平面透射电镜观测揭示了具有半圆柱形空隙的Ge中TD的独特行为（即TD弯曲以平行于SEG掩模和Si衬底）。

理论计算
图3显示了6种聚结Ge层中TD的计算轨迹:在这里，我们将孔径比（APR）定义为W窗口/（W窗口+ W掩模）。图3a显示了APR = 0.8的圆形SEG原点聚结Ge。在这里，2/6 TD 被困住。图3b显示了APR = 0.8的{113}面SEG原点聚结Ge。在这里，...

Watch this Scientific Journal Video about Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon at JoVE.co

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

提出了降低硅上半圆柱空隙的锗外延层螺纹位错（TD）密度的理论计算和实验验证。给出了基于TD与表面相互作用的计算方法，通过像力、TD测量和透射电子显微镜对TD的观测。

硅上半圆柱空隙锗外延层位错还原的理论计算和实验验证

Reduction of threading dislocation density (TDD) in epitaxial germanium (Ge) on silicon (Si) has been one of the most important challenges for the ...

theoretical-calculation-experimental-verification-for-dislocation

Universidad San Sebastian

Research

JoVE Journal

Engineering

2.1K 次观看.  The University of Tokyo. 提出了降低硅上半圆柱空隙的锗外延层螺纹位错（TD）密度的理论计算和实验验证。给出了基于TD与表面相互作用的计算方法，通过像力、TD测量和透射电子显微镜对TD的观测。 

视频: Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

通过硅直接晶圆粘接制造均匀纳米级腔

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

科研

工程学

Electron Channeling Contrast Imaging for Rapid III-V Heteroepitaxial Characterization

Misfit dislocations in heteroepitaxial layers of GaP grown on Si(001) substrates are characterized through use of electron channeling contrast imaging (ECCI) in a scanning electron microscope (SEM). ECCI allows for imaging of defects and crystallographic features under specific diffraction conditions, similar to that possible via plan-view transmission electron microscopy (PV-TEM). A particular advantage of the ECCI technique is that it requires little to no sample preparation, and indeed can use large area, as-produced samples, making it a considerably higher throughput characterization method than TEM. Similar to TEM, different diffraction conditions can be obtained with ECCI by tilting and rotating the sample in the SEM. This capability enables the selective imaging of specific defects, such as misfit dislocations at the GaP/Si interface, with high contrast levels, which are determined by the standard invisibility criteria. An example application of this technique is described wherein ECCI imaging is used to determine the critical thickness for dislocation nucleation for GaP-on-Si by imaging a range of samples with various GaP epilayer thicknesses. Examples of ECCI micrographs of additional defect types, including threading dislocations and a stacking fault, are provided as demonstration of its broad, TEM-like applicability. Ultimately, the combination of TEM-like capabilities &#8211; high spatial resolution and richness of microstructural data &#8211; with the convenience and speed of SEM, position ECCI as a powerful tool for the rapid characterization of crystalline materials.

The use of electron channeling contrast imaging in a scanning electron microscope to characterize defects in III-V/Si heteroexpitaxial thin films is described. This method yields similar results to plan-view transmission electron microscopy, but in significantly less time due to lack of required sample preparation.

电子通道造影的快速III-V异质特征

Misfit dislocations in heteroepitaxial layers of GaP grown on Si(001) substrates are characterized through use of electron channeling contrast imaging ...

Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

A procedure to measure the bulk lifetime (&#62;100 &#181;sec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min&#160;using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (&#60;1012 cm-3).

A RT liquid surface passivation technique to investigate the recombination activity of bulk silicon defects is described. For the technique to be successful, three critical steps are required: (i) chemical cleaning and etching of silicon, (ii) immersion of silicon in 15% hydrofluoric acid and (iii) illumination for 1 min.

光增强氢氟酸钝化:一个敏感的技术检测散装硅缺陷

A procedure to measure the bulk lifetime (&#62;100 &#181;sec) of silicon wafers by temporarily attaining a very high level of surface passivation when ...

Epitaxial Growth of Perovskite Strontium Titanate on Germanium via Atomic Layer Deposition

Atomic layer deposition (ALD) is a commercially utilized deposition method for electronic materials. ALD growth of thin films offers thickness control and conformality by taking advantage of self-limiting reactions between vapor-phase precursors and the growing film. Perovskite oxides present potential for next-generation electronic materials, but to-date have mostly been deposited by physical methods. This work outlines a method for depositing SrTiO3 (STO) on germanium using ALD. Germanium has higher carrier mobilities than silicon and therefore offers an alternative semiconductor material with faster device operation. This method takes advantage of the instability of germanium's native oxide by using thermal deoxidation to clean and reconstruct the Ge (001) surface to the 2&#215;1 structure. 2-nm thick, amorphous STO is then deposited by ALD. The STO film is annealed under ultra-high vacuum and crystallizes on the reconstructed Ge surface. Reflection high-energy electron diffraction (RHEED) is used during this annealing step to monitor the STO crystallization. The thin, crystalline layer of STO acts as a template for subsequent growth of STO that is crystalline as-grown, as confirmed by RHEED. In situ X-ray photoelectron spectroscopy is used to verify film stoichiometry before and after the annealing step, as well as after subsequent STO growth. This procedure provides framework for additional perovskite oxides to be deposited on semiconductors via chemical methods in addition to the integration of more sophisticated heterostructures already achievable by physical methods.

This work details the procedures for the growth and characterization of crystalline SrTiO3 directly on germanium substrates by atomic layer deposition. The procedure illustrates the ability of an all-chemical growth method to integrate oxides monolithically onto semiconductors for metal-oxide semiconductor devices.

锗通过原子层沉积钙钛矿型钛酸锶的外延生长

Atomic layer deposition (ALD) is a commercially utilized deposition method for electronic materials. ALD growth of thin films offers thickness control and ...

化学

Comprehensive Characterization of Extended Defects in Semiconductor Materials by a Scanning Electron Microscope

Extended defects such as dislocations and grain boundaries have a strong influence on the performance of microelectronic devices and on other applications of semiconductor materials. However, it is still under debate how the defect structure determines the band structure, and therefore, the recombination behavior of electron-hole pairs responsible for the optical and electrical properties of the extended defects. The present paper is a survey of procedures for the spatially resolved investigation of structural and of physical properties of extended defects in semiconductor materials with a scanning electron microscope (SEM). Representative examples are given for crystalline silicon. The luminescence behavior of extended defects can be investigated by cathodoluminescence (CL) measurements. They are particularly valuable because spectrally and spatially resolved information can be obtained simultaneously. For silicon, with an indirect electronic band structure, CL measurements should be carried out at low temperatures down to 5 K due to the low fraction of radiative recombination processes in comparison to non-radiative transitions at room temperature. For the study of the electrical properties of extended defects, the electron beam induced current (EBIC) technique can be applied. The EBIC image reflects the local distribution of defects due to the increased charge-carrier recombination in their vicinity. The procedure for EBIC investigations is described for measurements at room temperature and at low temperatures. Internal strain fields arising from extended defects can be determined quantitatively by cross-correlation electron backscatter diffraction (ccEBSD). This method is challenging because of the necessary preparation of the sample surface and because of the quality of the diffraction patterns which are recorded during the mapping of the sample. The spatial resolution of the three experimental techniques is compared.

The optical, electrical, and structural properties of dislocations and of grain boundaries in semiconductor materials can be determined by experiments performed in a scanning electron microscope. Electron microscopy has been used to investigate cathodoluminescence, electron beam induced current, and diffraction of backscattered electrons.

通过扫描电子显微镜在半导体材料的扩展缺陷的全面表征

Extended defects such as dislocations and grain boundaries have a strong influence on the performance of microelectronic devices and on other applications ...

Probing C84-embedded Si Substrate Using Scanning Probe Microscopy and Molecular Dynamics

This paper reports an array-designed C84-embedded Si substrate fabricated using a controlled self-assembly method in an ultra-high vacuum chamber. The characteristics of the C84-embedded Si surface, such as atomic resolution topography, local electronic density of states, band gap energy, field emission properties, nanomechanical stiffness, and surface magnetism, were examined using a variety of surface analysis techniques under ultra, high vacuum (UHV) conditions as well as in an atmospheric system. Experimental results demonstrate the high uniformity of the C84-embedded Si surface fabricated using a controlled self-assembly nanotechnology mechanism, represents an important development in the application of field emission display (FED), optoelectronic device fabrication, MEMS cutting tools, and in efforts to find a suitable replacement for carbide semiconductors. Molecular dynamics (MD) method with semi-empirical potential can be used to study the nanoindentation of C84-embedded Si substrate. A detailed description for performing MD simulation is presented here. Details for a comprehensive study on mechanical analysis of MD simulation such as indentation force, Young&#39;s modulus, surface stiffness, atomic stress, and atomic strain are included. The atomic stress and von-Mises strain distributions of the indentation model can be calculated to monitor deformation mechanism with time evaluation in atomistic level.

Probing C84-embedded Si Substrate Using Scanning Probe Microscopy and Molecular Dynamics

This paper reports the nanomaterial fabrication of a fullerene Si substrate inspected and verified by nanomeasurements and molecular dynamic simulation.

探测ç<sub&gt; 84</sub&gt; - 嵌入式硅衬底利用扫描探针显微镜和分子动力学

This paper reports an array-designed C84-embedded Si substrate fabricated using a controlled self-assembly method in an ultra-high vacuum chamber. The ...

A Novel Method for In Situ Electromechanical Characterization of Nanoscale Specimens

Electrically assisted deformation (EAD) is increasingly being used to improve the formability of metals during processes such as sheet metal rolling and forging. Adoption of this technique is proceeding despite disagreement concerning the underlying mechanism responsible for EAD. The experimental procedure described herein enables a more explicit study compared to previous EAD research by removing thermal effects, which are responsible for disagreement in interpreting previous EAD results. Furthermore, as the procedure described here enables EAD observation in situ and in real time in a transmission electron microscope (TEM), it is superior to existing post-mortem methods that observe EAD effects post-test. Test samples consist of a single crystal copper (SCC) foil having a free-standing tensile test section of nanoscale thickness, fabricated using a combination of laser and ion beam milling. The SCC is mounted to an etched silicon base that provides mechanical support and electrical isolation while serving as a heat sink. Using this geometry, even at high current density (~3,500 A/mm2), the test section experiences a negligible temperature increase (&#60;0.02 &#176;C), thus eliminating Joule heating effects. Monitoring material deformation and identifying the corresponding changes to microstructures, e.g. dislocations, are accomplished by acquiring and analyzing a series of TEM images. Our sample preparation and in situ experiment procedures are robust and versatile as they can be readily utilized to test materials with different microstructures, e.g., single and polycrystalline copper.

A Novel Method for In Situ Electromechanical Characterization of Nanoscale Specimens

Isolating electrical and thermal effects on electrically assisted deformation (EAD) is very difficult using macroscopic samples. Metallic sample micro- and nanostructures together with a custom test procedure have been developed to evaluate the impact of applied current on the formation without joule heating and evolution of dislocations on these samples.

一种新的方法<em&gt;原位</em&gt;纳米级样品的机电表征

Electrically assisted deformation (EAD) is increasingly being used to improve the formability of metals during processes such as sheet metal rolling and ...

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

To form a coherent quantum transport in hybrid superconductor-semiconductor (S-Sm) junctions, the formation of a homogeneous and barrier-free interface between two different materials is necessary. The S-Sm junction with high interface transparency will then facilitate the observation of the induced hard superconducting gap, which is the key requirement to access the topological phases (TPs) and observation of exotic quasiparticles such as Majorana zero modes (MZM) in hybrid systems. A material platform that can support observation of TPs and allows the realization of complex and branched geometries is therefore highly demanding in quantum processing and computing science and technology. Here, we introduce a two-dimensional material system and study the proximity induced superconductivity in semiconducting two-dimensional electron gas (2DEG) that is the basis of a hybrid quantum integrated circuit (QIC). The 2DEG is a 30 nm thick In0.75Ga0.25As quantum well that is buried between two In0.75Al0.25As barriers in a heterostructure. Niobium (Nb) films are used as the superconducting electrodes to form Nb- In0.75Ga0.25As -Nb Josephson junctions (JJs) that are symmetric, planar and ballistic. Two different approaches were used to form the JJs and QICs. The long junctions were fabricated photolithographically, but e-beam lithography was used for short junctions&#8217; fabrication. The coherent quantum transport measurements as a function of temperature in the presence/absence of magnetic field B are discussed. In both device fabrication approaches, the proximity induced superconducting properties were observed in the In0.75Ga0.25As 2DEG. It was found that e-beam lithographically patterned JJs of shorter lengths result in observation of induced superconducting gap at much higher temperature ranges. The results that are reproducible and clean suggesting that the hybrid 2D JJs and QICs based on In0.75Ga0.25As quantum wells could be a promising material platform to realize the real complex and scalable electronic and photonic quantum circuitry and devices.

Quantum integrated circuits (QICs) consisting of array of planar and ballistic Josephson junctions (JJs) based on In0.75Ga0.25As two-dimensional electron gas (2DEG) is demonstrated. Two different methods for fabrication of the two-dimensional (2D) JJs and QICs are discussed followed by the demonstration of quantum transport measurements in sub-Kelvin temperatures.

超导二维电子气体平台上的可扩展量子集成电路

To form a coherent quantum transport in hybrid superconductor-semiconductor (S-Sm) junctions, the formation of a homogeneous and barrier-free interface ...

Developing High Performance GaP/Si Heterojunction Solar Cells

To improve the efficiency of Si-based solar cells beyond their Shockley-Queisser limit, the optimal path is to integrate them with III-V-based solar cells. In this work, we present high performance GaP/Si heterojunction solar cells with a high Si minority-carrier lifetime and high crystal quality of epitaxial GaP layers. It is shown that by applying phosphorus (P)-diffusion layers into the Si substrate and a SiNx layer, the Si minority-carrier lifetime can be well-maintained during the GaP growth in the molecular beam epitaxy (MBE). By controlling the growth conditions, the high crystal quality of GaP was grown on the P-rich Si surface. The film quality is characterized by atomic force microscopy and high-resolution x-ray diffraction. In addition, MoOx was implemented as a hole-selective contact that led to a significant increase in the short-circuit current density. The achieved high device performance of the GaP/Si heterojunction solar cells establishes a path for further enhancement of the performance of Si-based photovoltaic devices.

Here, we present a protocol to develop high-performance GaP/Si heterojunction solar cells with a high Si minority-carrier lifetime.

研制高性能的 gap-硅异构太阳能电池

To improve the efficiency of Si-based solar cells beyond their Shockley-Queisser limit, the optimal path is to integrate them with III-V-based solar ...

3D Depth Profile Reconstruction of Segregated Impurities Using Secondary Ion Mass Spectrometry

The presented protocol combines excellent detection limits (1 ppm to 1 ppb) using secondary ion mass spectrometry (SIMS) with reasonable spatial resolution (~1 &#181;m). Furthermore, it describes how to obtain realistic three-dimensional (3D) distributions of segregated impurities/dopants in solid state materials. Direct 3D depth profile reconstruction is often difficult to achieve due to SIMS-related measurement artifacts. Presented here is a method to identify and solve this challenge. Three major issues are discussed, including the i) nonuniformity of the detector being compensated by flat-field correction; ii) vacuum background contribution (parasitic oxygen counts from residual gases present in the analysis chamber) being estimated and subtracted; and iii)&#160;performance of all steps within a stable timespan of the primary ion source. Wet chemical etching is used to reveal the position and types of dislocation in a material, then the SIMS result is superimposed on images obtained via scanning electron microscopy (SEM). Thus, the position of agglomerated impurities can be related to the position of certain defects. The method is fast and does not require sophisticated sample preparation stage; however, it requires a high-quality, stable ion source, and the entire measurement must be performed quickly to avoid deterioration of the primary beam parameters.

The presented method describes how to identify and solve measurement artifacts related to secondary ion mass spectrometry as well as obtain realistic 3D distributions of impurities/dopants in solid state materials.

硅上半圆柱空隙锗外延层位错还原的理论计算和实验验证

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