Name: a standard and reliable method to fabricate two-dimensional nanoelectronics
Uploaded: 2018-08-28T13:00:00.000+00:00
Duration: 7 min 12 s
Description: Watch this Scientific Journal Video about A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics at JoVE.com

这项工作得到了台湾国家科学委员会的支持。最多105-2112 米-003-016 MY3。这项工作还部分由国家纳米设备实验室和国立台湾大学电气工程电子梁实验室支持。

1. 2D 准异质结晶体管制造工艺
<ol><li>准备商业 c 平面蓝宝石。<ol>
<li>用丙酮清洗全单面抛光蓝宝石 (2 英寸)。</li>
		<li>用异丙醇冲洗蓝宝石基底。</li>
	</ol></li>
	<li>在热壁炉中使用 CVD, 在蓝宝石基底上生长 MoS2 。<ol>
<li>将0.6 克三氧化钼 (MoO3) 粉放在位于炉膛加热区中心的石英船上。将蓝宝石衬底置于含有 MoO3粉末的石英船旁边。</li>
		<li>在炉子上游的另一只石英船上制备硫磺粉。在反应过程中保持温度在190摄氏度。</li>
		<li>使用氩 (Ar = 70 sccm, 40 乇) 气体流, 使 S 和 MoO3蒸气到蓝宝石基体, 同时加热中心区到750°c。</li>
		<li>保持加热区, 达到所需的750摄氏度的生长温度, 15 分钟, 然后自然冷却炉到室温。</li>
	</ol></li>
	<li>执行 EBL。 注: 在蓝宝石基底上的所有 EBL 过程中, 溅射沉积约 5 nm 的薄金。<ol>
<li>使用光学显微镜识别 MoS2单层薄片的区域, 然后使用设计软件 (AutoCAD) 为该特定区域设计条纹图案布局。</li>
		<li>自旋涂层光刻胶 (PR), 例如有机玻璃甲基丙烯酸甲酯 (PMMA) 或 P015, 上面的样品在 2000 rpm 六十年代 (室温)。确保 PR 覆盖整个样品后, 自旋涂层。</li>
		<li>加热样品 (软烘烤) 在100°c 在九十年代为了蒸发溶剂在 PR 和增强黏附力。</li>
		<li>将步骤1.3.1 中的模式布局转换为特定文件 (例如: GDS 文件), 然后将其上载到 EBL 软件中。</li>
		<li>根据布局中线条的宽度确定理想的电子束剂量。 注: 对于宽度小于1µm 的线宽, 理想的电子束剂量为110µC/厘米2;1至5µm 线宽, 剂量为100µC/厘米2;对于宽度大于5µm 的线宽, 剂量为80µC/厘米2。</li>
		<li>开始将样品暴露在电子束上。</li>
		<li>在样品曝光后应用曝光后烘烤 (PEB), 以减少驻波效应。在九十年代将样品加热120摄氏度。</li>
		<li>将四甲基氢氧化 TMAH 2.38% 作为开发人员使用。将样品浸入 TMAH 八十年代. 用200毫升的去离子水冲洗 TMAH 十年代。</li>
		<li>检查该模式是否良好的光学显微学发展。</li>
		<li>进行硬烘烤, 以摆脱额外的水在公关. 在九十年代将样品加热110摄氏度。</li>
	</ol></li>
	<li>定义条纹结构使用 50 W 氧 (O2) 等离子蚀刻 (1st蚀刻) 三十年代至2分钟, 并删除 PR 使用50毫升丙酮。</li>
	<li>在目标位置上使用 CVD 来生长钨硒醚 (WSe2), 这将导致在蓝宝石基底上已经存在的 MoS2条纹之间的 WSe2层的首选增长。<ol>
<li>将0.6 克三氧化钨 (禾3) 粉放在位于炉膛加热区中心的石英船上。将蓝宝石衬底置于含禾3粉的石英船旁边。</li>
		<li>在炉子上游的另一只石英船上制备硒 (硒) 粉。在反应过程中保持温度在260摄氏度。</li>
		<li>使用 ar/小时2 (ar = 90 sccm, H2 = 6 sccm, 20 乇) 气体流动带来 Se 和禾3蒸气到蓝宝石基体, 同时加热中心区到925°c。</li>
		<li>保持加热区, 达到所需的925摄氏度的生长温度, 15 分钟, 然后自然冷却炉到室温。</li>
	</ol></li>
	<li>制造金属垫阵列和对准标记。<ol>
<li>用光刻图案技术覆盖金属垫阵列的图案并对准标记。</li>
		<li>用电子枪蒸发器沉积 20 nm/60 纳米钛/Au。 注: 金用于避免金属衬垫的氧化。</li>
		<li>准备并将样品浸入100毫升丙酮中, 以溶解 PR 并进行升降。通过光学显微镜监测整个过程, 直到金属垫片变得明显时, 摇动并吹干丙酮。</li>
	</ol></li>
	<li>执行另一个 EBL 进程, 将功能区形状模式覆盖在 MoS2-WSe2异质结的顶部。<ol>
<li>使用光学显微镜测量 MoS2-WSe2异质结中的目标位置与对准标记之间的坐标位移, 并根据这些测量结果设计使用软件 (AutoCAD) 的带状形状布局。</li>
		<li>自旋涂层 PR, 例如 PMMA 或 P015, 在样品的顶部在 2000 rpm 六十年代 (室温)。确保 PR 覆盖整个样品后, 自旋涂层。</li>
		<li>加热样品 (软烘烤) 在100°c 在九十年代为了蒸发溶剂在 PR 和增强黏附力。</li>
		<li>将步骤1.7.1 中的模式布局转换为特定文件 (例如: GDS 文件), 然后将其上载到 EBL 软件中。</li>
		<li>根据布局中线条的宽度确定理想的电子束剂量。 注: 对于宽度小于1µm 的线宽, 理想的电子束剂量为110µC/厘米2;1至5µm 线宽, 剂量为100µC/厘米2;对于宽度大于5µm 的线宽, 剂量为80µC/厘米2。</li>
		<li>设置 EBL 机, 使在蓝宝石衬底上的对准标记位置与布局中的对应相匹配。</li>
		<li>开始将样品暴露在电子束上。</li>
		<li>在样品曝光后应用 PEB, 以减少驻波效应。在九十年代将样品加热120摄氏度。</li>
		<li>使用 TMAH 2.38% 作为开发人员。将样品浸入 TMAH 八十年代. 用200毫升去离子水冲洗 TMAH 十年代。</li>
		<li>检查该模式是否良好的光学显微学发展。</li>
		<li>进行硬烘烤, 以摆脱额外的水在公关. 在九十年代将样品加热110摄氏度。</li>
	</ol></li>
	<li>使用 O2等离子蚀刻 (2和蚀刻) 来定义带状形状的横向异质结, 并通过丙酮去除 PR。</li>
	<li>执行 EBL 过程覆盖钛/金金属电极的模式。<ol>
<li>用光学显微镜测量 MoS2-WSe2异质结中目标位置与对准标记之间的坐标位移, 并根据这些测量方法设计金属电极布局。</li>
		<li>自旋涂层 PR, 例如 PMMA 或 P015, 在样品的顶部在 2000 rpm 六十年代 (室温)。确保 PR 覆盖整个样品后, 自旋涂层。</li>
		<li>加热样品 (软烘烤) 在100°c 在九十年代为了蒸发溶剂在 PR 和增强黏附力。</li>
		<li>将步骤1.9.1 中的模式布局转换为特定文件 (例如: GDS 文件), 然后将其上载到 EBL 软件中。</li>
		<li>根据金属线在布局中的宽度确定理想的电子束剂量。 注: 对于窄于1µm 的金属线宽度, 理想的电子束剂量为110µC/厘米2;1至5µm 线宽, 剂量为100µC/厘米2;对于宽度大于5µm 的线宽, 剂量为80µC/厘米2。</li>
		<li>设置 EBL 机, 使蓝宝石衬底上的对准标记位置与布局中的对应相匹配。</li>
		<li>开始将样品暴露在电子束上。</li>
		<li>在样品曝光后应用 PEB, 以减少驻波效应。在九十年代将样品加热120摄氏度。</li>
		<li>使用 TMAH 2.38% 作为开发人员。将样品浸入 TMAH 八十年代. 用200毫升去离子水冲洗 TMAH 十年代。</li>
		<li>检查该模式是否良好的光学显微学发展。</li>
		<li>进行硬烘烤, 以摆脱额外的水在公关. 在九十年代将样品加热110摄氏度。</li>
	</ol></li>
	<li>执行钛/金金属沉积和升降<ol>
<li>用电子枪蒸发器沉积钛/金, 其厚度小于100纳米, 否则, 将很难去除 PR 和不需要的金属的升降。</li>
		<li>准备并将样品浸入100毫升丙酮中, 以溶解 PR 并进行升降。通过光学显微镜监测整个过程, 直到只剩下金属线和衬垫, 才能震动和吹干丙酮。</li>
	</ol></li>
	<li>执行步骤1.9 中的 EBL 过程, 但覆盖 Pd/au 金属电极的模式, 而不是 Ti/au。</li>
	<li>执行步骤1.10 中的金属沉积和升降过程, 但将 Pd/au 代替 Ti/au。</li>
</ol>2. 2D 后门控晶体管制造工艺
<ol><li>准备背面门控硅/2基板与对准标记。<ol>
<li>准备国产或商用2/硅基板。</li>
		<li>使用光刻或 EBL 图案技术来定义对齐标记。</li>
		<li>对2/硅基板进行反应离子蚀刻 (离子刻蚀), 直到目标区域的总深度达到 1000 nm, 并通过 O2等离子去除 PR, 以显示形成的对准标记。</li>
		<li>使用光刻图案技术覆盖金属垫阵列的图案。</li>
		<li>用电子枪蒸发器沉积 20 nm/60 纳米钛/Au。 注: 金用于避免金属垫的氧化。</li>
		<li>准备并将样品浸入100毫升丙酮中, 以溶解 PR 并进行升降。在用光学显微镜监测整个过程时, 摇动和吹丙酮, 直到金属垫片变得明显。</li>
	</ol>
</li>
	<li>在热壁炉上对蓝宝石基底上的 MoS2进行 CVD。<ol>
<li>将0.6 克 MoO3粉末放在位于熔炉加热区中心的石英船上。将蓝宝石衬底置于含有 MoO3粉末的石英船旁边。</li>
		<li>在炉子上游的一条独立的石英船上制备 S 粉末。在反应过程中保持温度在190摄氏度。</li>
		<li>使用氩 (Ar = 70 sccm, 40 乇) 气体流, 使 S 和 MoO3蒸气到蓝宝石基体, 同时加热中心区到750°c。</li>
		<li>保持加热区, 达到所需的750摄氏度的生长温度, 15 分钟, 然后自然冷却炉到室温。</li>
	</ol>
</li>
	<li>将 MoS2从蓝宝石传输到后端门式2/Si 衬底。<ol>
<li>自旋外套 PMMA 以 3500 rpm 的自转速度三十年代在 MoS2影片之上。</li>
		<li>烘烤 MoS2/蓝宝石样品在120°c 为3分钟, 以加强 PMMA 涂层。</li>
		<li>将 mos2/蓝宝石样品浸入50毫升氨溶液 (14.5%), 约30分钟至 2 h, 以将 mos2胶片与蓝宝石基底隔开。</li>
		<li>拿起胶卷, 把它转移到2/Si 衬底。</li>
		<li>烘烤 mos2/2/Si 样品, 以增强 mos2和2层之间的附着力。将样品加热120摄氏度, 约30分钟至1小时。</li>
		<li>用30毫升丙酮清洗有机玻璃, 大约30分钟到2小时, 除去 PMMA。</li>
		<li>用异丙醇冲洗样品, 用氮气吹干。</li>
	</ol>
</li>
	<li>执行 EBL。 注: EBL 过程中, 由于 Si 的导电性, 在2/硅基板上没有沉积薄金。<ol>
<li>用光学显微镜测量目标位置与对准标记之间的坐标位移, 并根据这些测量结果设计出金属电极的图案布局。 注: 金属电极将 MoS2样品中的靶点连接至2/Si 衬底的金属垫片。</li>
		<li>自旋涂层 PR, 例如 PMMA 或 P015, 在样品的顶部在 2000 rpm 六十年代 (室温)。确保 PR 覆盖了整个样品。</li>
		<li>加热样品 (软烘烤) 在100°c 在九十年代为了蒸发溶剂在 PR 和增强黏附力。</li>
		<li>将步骤2.4.1 中的模式布局转换为特定文件 (例如: GDS 文件), 然后将其上载到 EBL 软件中。</li>
		<li>根据金属线在布局中的宽度确定理想的电子束剂量。 注: 对于窄于1µm 的金属线宽度, 理想的电子束剂量为110µC/厘米2;1至5µm 线宽, 剂量为100µC/厘米2;对于宽度大于5µm 的线宽, 剂量为80µC/厘米2。</li>
		<li>设置 EBL 机, 使在 Si/2衬底上的对准标记位置与布局中的对应相匹配。</li>
		<li>开始将样品暴露在电子束上。</li>
		<li>在样品曝光后应用 PEB, 以减少驻波效应。在九十年代将样品加热120摄氏度。</li>
		<li>使用 TMAH 2.38% 作为开发人员。将样品浸入 TMAH 八十年代. 用200毫升的去离子水冲洗 TMAH 十年代。</li>
		<li>检查该模式是否良好的光学显微学发展。</li>
		<li>进行硬烘烤, 以摆脱额外的水在公关. 在九十年代将样品加热110摄氏度。</li>
	</ol>
</li>
	<li>执行金金属沉积和升降<ol>
<li>用电子枪蒸发器沉积金金属, 其厚度小于100纳米, 否则将难以去除 PR 和不需要的金属。</li>
		<li>准备并将样品浸入100毫升丙酮中, 以溶解 PR 并进行升降。在通过光学显微镜监测过程时, 摇动和吹丙酮, 直到只有金属线和衬垫。</li>
	</ol>
</li>
</ol>

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H., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Polymer-free+patterning+of+graphene+at+sub-10-nm+scale+by+low-energy+repetitive+electron+beam.">Polymer-free patterning of graphene at sub-10-nm scale by low-energy repetitive electron beam.</a> Small. 10 (22), 4778-4784 (2014).</li><li>Romero, M. F., Bosca, A., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Impact+of+2D-Graphene+on+SiN+Passivated+AlGaN/GaN+MIS-HEMTs+Under+Mist+Exposure.">Impact of 2D-Graphene on SiN Passivated AlGaN/GaN MIS-HEMTs Under Mist Exposure.</a> IEEE Electron Device Letters. 38 (10), 1441-1444 (2017).</li><li>Blaschke, B. M., Tort-Colet, N., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Mapping+brain+activity+with+flexible+graphene+micro-transistors.">Mapping brain activity with flexible graphene micro-transistors.</a> 2D Materials. 4 (2), 25040 (2017).</li><li>Zhu, Z., Murtaza, I., Meng, H., Huang, W. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Thin+film+transistors+based+on+two+dimensional+graphene+and+graphene/semiconductor+heterojunctions.">Thin film transistors based on two dimensional graphene and graphene/semiconductor heterojunctions.</a> RSC Advances. 7 (28), 17387-17397 (2017).</li><li>Kim, S. J., Choi, K., Lee, B., Kim, Y., Hong, B. H. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Materials+for+Flexible,+Stretchable+Electronics:+Graphene+and+2D+Materials.">Materials for Flexible, Stretchable Electronics: Graphene and 2D Materials.</a> Annual Review of Materials Research. 45 (1), 63-84 (2015).</li><li>Manzeli, S., Ovchinnikov, D., Pasquier, D., Yazyev, O. V., Kis, A. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=2D+transition+metal+dichalcogenides.">2D transition metal dichalcogenides.</a> Nature Reviews Materials. 2, (2017).</li><li>Kolobov, A. V., Tominaga, J. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=.">.</a> Emerging Applications of 2D TMDCs. 239, 473-512 (2016).</li><li>Nguyen, L. N., Lan, Y. W., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Resonant+tunneling+through+discrete+quantum+states+in+stacked+atomic-layered+MoS2.">Resonant tunneling through discrete quantum states in stacked atomic-layered MoS2.</a> Nano Letters. 14 (5), 2381-2386 (2014).</li><li>Torres, C. M., Lan, Y. W., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=High-Current+Gain+Two-Dimensional+MoS2-Base+Hot-Electron+Transistors.">High-Current Gain Two-Dimensional MoS2-Base Hot-Electron Transistors.</a> Nano Letters. 15 (12), 7905-7912 (2015).</li><li>Jariwala, D., Sangwan, V. K., Lauhon, L. J., Marks, T. J., Hersam, M. C. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Emerging+Device+Applications+for+Semiconducting+Two-Dimensional+Transition+Metal+Dichalcogenides.">Emerging Device Applications for Semiconducting Two-Dimensional Transition Metal Dichalcogenides.</a> ACS Nano. 8 (2), 1102-1120 (2014).</li><li>Choi, W., Choudhary, N., Han, G. H., Park, J., Akinwande, D., Lee, Y. H. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Recent+development+of+two-dimensional+transition+metal+dichalcogenides+and+their+applications.">Recent development of two-dimensional transition metal dichalcogenides and their applications.</a> Materials Today. 20 (3), 116-130 (2017).</li><li>Xiao, H. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=.">.</a> Introduction to Semiconductor Manufacturing Technology, Second Edition. , (2012).</li><li>Lin, C. Y., Zhu, X., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Atomic-Monolayer+Two-Dimensional+Lateral+Quasi-Heterojunction+Bipolar+Transistors+with+Resonant+Tunneling+Phenomenon.">Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.</a> ACS Nano. 11 (11), 11015-11023 (2017).</li><li>Qi, J., Lan, Y. W., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Piezoelectric+effect+in+chemical+vapour+deposition-grown+atomic-monolayer+triangular+molybdenum+disulfide+piezotronics.">Piezoelectric effect in chemical vapour deposition-grown atomic-monolayer triangular molybdenum disulfide piezotronics.</a> Nature Communications. 6, (2015).</li></ol>

作者没有什么可透露的。

本文介绍了基于纳米尺度的2D 材料制作新型电子产品的具体程序。由于每种应用的样品制备程序有差异, 重叠过程被视为协议。电子束模式结合材料定位确定和金属电极的定义, 因此在这里充当协议。在上述两种类型的器件中, 提出了从湿式转移单晶 MoS2薄膜到2/硅基片上的2D 后门控晶体管的全过程, 以及在金属升降时的结束。在2D 后门控晶体管上给出焦点的原因是改进的2D 材料基场...

自过去几十年以来, 人类经历了晶体管大小的快速缩小, 因此, 集成电路 (ICs) 中晶体管的数量呈指数上升。这保持了硅基互补金属氧化物半导体 (CMOS) 技术1的持续发展。此外, 这一目前的规模和性能的制造设备仍在轨道上的摩尔定律, 其中指出, 电子芯片上的晶体管数量, 以及其性能, 大约每两年2倍。CMOS 晶体管是存在于大多数, 即使不是全部, 电子设备在市场上可用, 从而使它成为人类生活的一个组成部分。由于这一点, 不断的需求, 以改善芯片的规模和性能, 一直推动制造商遵循摩尔的法律轨道。
不幸的是, 摩尔定律似乎快要结束了, 因为更多的硅电路被压缩到一个小面积2的时候产生的热量。这就要求新类型的材料可以提供与硅相同的性能, 如果不是更好, 则可以在相对较小的范围内实现。近年来, 新材料已成为许多材料科学研究的主题。此类材料为一维 (1D) 碳纳米管3、4、5、6、7、2D 石墨烯8、9、10、11,12、过渡金属 dichalcogenides (TMDs)13、14、15、16、17、18, 是优秀的候选者, 可作为替代硅基 CMOS, 并继续摩尔的法律轨道。
制作小规模设备需要仔细确定材料的位置, 以成功地进行其他制造技术, 如光刻和金属电极的定义。因此, 本文提出的方法是为了满足这一需要而设计的。与传统的半导体制造技术19相比, 本文提出的方法适合于小尺寸器件的开发, 在寻找材料的位置方面需要更多的关注。该方法的目的是可靠地制造2D 纳米材料器件, 如2D 后门控晶体管和 Q 双, 使用标准制造工艺。这可以成为未来 nanodevice 发展的平台, 因为它为未来先进的纳米级器件的生产铺平了道路。
在程序部分, 详细讨论了2D 材料基器件的制造工艺, 即 Q HBT 和2D 后置门式晶体管。电子束模式结合材料定位确定和金属电极定义包括该协议, 因为它们在上述两个过程中都是必需的。第1部分讨论了 Q-双20的分步制作过程;和2部分展示了一种普遍的方法, 获得化学气相沉积 (CVD) 二硫化钼 (MoS2) 后门控晶体管从转移到推力21, 这已经完全显示在本文中。详细的流程流程如下所示 (图 1)。

<table><tbody><tr><td>E-gun Evaporator</td><td>AST</td><td>PEVA 600I</td><td></td></tr><tr><td>Au slug, 99.99%</td><td>Well-Being Enterprise Co</td><td>N/A</td><td></td></tr><tr><td>Ti slug, 99.99%</td><td>Well-Being Enterprise Co</td><td>N/A</td><td></td></tr><tr><td>E-beam Lithography System</td><td>Elionix</td><td>ELS7500-EX</td><td></td></tr><tr><td>Cold Wall CVD System</td><td>Sulfur Science</td><td>SCW600S</td><td></td></tr><tr><td>C-plane Sapphire substrate</td><td>Summit-Tech</td><td>X171999</td><td>(0001) &amp;plusmn; 0.2 &amp;deg; one side polished</td></tr><tr><td>100 nm SiO&lt;sub&gt;2&lt;/sub&gt;/Si</td><td></td><td></td><td>Fabricated in NDL</td></tr><tr><td>Ammonia Solution</td><td>BASF</td><td>Ammonia Solution 28% Selectipur</td><td></td></tr><tr><td>Molybdenum (Mo), 99.95%</td><td>Summit-Tech</td><td>N/A</td><td></td></tr><tr><td>Tungsten (W), 99.95%</td><td>Summit-Tech</td><td>N/A</td><td></td></tr><tr><td>Sulfur (S), 99.5%</td><td>Sigma-Aldrich</td><td>13803</td><td></td></tr><tr><td>Polymethyl Methacrylate (PMMA)</td><td>Microchem</td><td>8110788</td><td>Use for transfer process</td></tr><tr><td>Spin Coater</td><td>Laurell</td><td>WS 400B 6NPP LITE</td><td></td></tr><tr><td>Acetone</td><td>BASF</td><td>Acetone EL Selectipur</td><td></td></tr><tr><td>Isopropanol (IPA)</td><td>BASF</td><td>2-Propanol UPS</td><td></td></tr><tr><td>Photo Resist for EBL</td><td>TOK</td><td>TDUR-P-015</td><td></td></tr><tr><td>Plasma Cleaner</td><td>Harrick Plasma</td><td>PDC-32G</td><td>Oxygen plasma</td></tr></tbody></table>

a standard and reliable method to fabricate two-dimensional nanoelectronics

二维 (2D) 材料由于其独特的性能和潜在的应用, 引起了人们的极大关注。由于2D 材料的硅片规模合成尚处于起步阶段, 科学家们不能完全依靠传统的半导体技术进行相关研究。微妙的过程从定位材料到电极的定义需要很好的控制。本文介绍了制造纳米电子所需的通用制造协议, 如2D 准异质结双极晶体管 (Q HBT) 和2D 后向门控晶体管。该协议包括材料位置的确定, 电子束光刻 (EBL), 金属电极的定义,等等。文中还介绍了这些装置的制作过程的逐步叙述。结果表明, 所研制的器件均具有较高的重复性和高的性能。这项工作揭示了制备2D 纳米电子的流程流程的全面描述, 使研究小组能够访问这些信息, 并为未来的电子学铺平道路。

该装置的制造工艺已应用于相应的作者研究, 涉及2D 材料器件的开发。在这一部分中, 本文给出的一些研究结果表明了上述协议的有效性。以2-MoS2 Q HBT20为例, 选取了一层侧向 WSe。使用协议中详细介绍的标准设备制造过程, heterojunctions 了单层侧向 WSe2-MoS2 (图 2a), 然后由 Q HBT 的形成进行。金属接触沉积?...

Watch this Scientific Journal Video about A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics at JoVE.com

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

本文旨在为未来低维电子学的开发提供一个标准可靠的制造程序。

制造二维电子学的标准可靠方法

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

a-standard-reliable-method-to-fabricate-two-dimensional

Universidad San Sebastian

Research

JoVE Journal

Engineering

9.5K 次观看.  National Taiwan Normal University. 本文旨在为未来低维电子学的开发提供一个标准可靠的制造程序。

视频: A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

制造由Nanoskiving Nanogaps的

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

科研

化学

A Method to Fabricate Disconnected Silver Nanostructures in 3D

The standard nanofabrication toolkit includes techniques primarily aimed at creating 2D patterns in dielectric media. Creating metal patterns on a submicron scale requires a combination of nanofabrication tools and several material processing steps. For example, steps to create planar metal structures using ultraviolet photolithography and electron-beam lithography can include sample exposure, sample development, metal deposition, and metal liftoff. To create 3D metal structures, the sequence is repeated multiple times. The complexity and difficulty of stacking and aligning multiple layers limits practical implementations of 3D metal structuring using standard nanofabrication tools. Femtosecond-laser direct-writing has emerged as a pre-eminent technique for 3D nanofabrication.1,2 Femtosecond lasers are frequently used to create 3D patterns in polymers and glasses.3-7 However, 3D metal direct-writing remains a challenge. Here, we describe a method to fabricate silver nanostructures embedded inside a polymer matrix using a femtosecond laser centered at 800 nm. The method enables the fabrication of patterns not feasible using other techniques, such as 3D arrays of disconnected silver voxels.8 Disconnected 3D metal patterns are useful for metamaterials where unit cells are not in contact with each other,9 such as coupled metal dot10,11or coupled metal rod12,13 resonators. Potential applications include negative index metamaterials, invisibility cloaks, and perfect lenses.
In femtosecond-laser direct-writing, the laser wavelength is chosen such that photons are not linearly absorbed in the target medium. When the laser pulse duration is compressed to the femtosecond time scale and the radiation is tightly focused inside the target, the extremely high intensity induces nonlinear absorption. Multiple photons are absorbed simultaneously to cause electronic transitions that lead to material modification within the focused region. Using this approach, one can form structures in the bulk of a material rather than on its surface.
Most work on 3D direct metal writing has focused on creating self-supported metal structures.14-16 The method described here yields sub-micrometer silver structures that do not need to be self-supported because they are embedded inside a matrix. A doped polymer matrix is prepared using a mixture of silver nitrate (AgNO3), polyvinylpyrrolidone (PVP) and water (H2O). Samples are then patterned by irradiation with an 11-MHz femtosecond laser producing 50-fs pulses. During irradiation, photoreduction of silver ions is induced through nonlinear absorption, creating an aggregate of silver nanoparticles in the focal region. Using this approach we create silver patterns embedded in a doped PVP matrix. Adding 3D translation of the sample extends the patterning to three dimensions.

Femtosecond-laser direct-writing is frequently used to create three-dimensional (3D) patterns in polymers and glasses. However, patterning metals in 3D remains a challenge. We describe a method for fabricating silver nanostructures embedded inside a polymer matrix using a femtosecond laser centered at 800 nm.

一个断开连接的银纳米结构的方法来制作的3D

The standard nanofabrication toolkit includes  techniques primarily aimed at creating 2D patterns in dielectric media. Creating  metal patterns on a ...

工程学

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and entanglement, to solve certain problems exponentially faster than with the best known algorithms on a classical computer. Gate-defined lateral quantum dots on GaAs/AlGaAs are one of many avenues explored for the implementation of a qubit. When properly fabricated, such a device is able to trap a small number of electrons in a certain region of space. The spin states of these electrons can then be used to implement the logical 0 and 1 of the quantum bit. Given the nanometer scale of these quantum dots, cleanroom facilities offering specialized equipment- such as scanning electron microscopes and e-beam evaporators- are required for their fabrication. Great care must be taken throughout the fabrication process to maintain cleanliness of the sample surface and to avoid damaging the fragile gates of the structure. This paper presents the detailed fabrication protocol of gate-defined lateral quantum dots from the wafer to a working device. Characterization methods and representative results are also briefly discussed. Although this paper concentrates on double quantum dots, the fabrication process remains the same for single or triple dots or even arrays of quantum dots. Moreover, the protocol can be adapted to fabricate lateral quantum dots on other substrates, such as Si/SiGe.

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

纳米加工门定义的GaAs / AlGaAs多量子点横向

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

超高密度垂直对齐的任意基质的小分子有机纳米线阵列

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.

The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

硅金属 - 氧化物 - 半导体量子点单电子泵

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by ...

Atomically Traceable Nanostructure Fabrication

Reducing the scale of etched nanostructures below the 10 nm range eventually will require an atomic scale understanding of the entire fabrication process being used in order to maintain exquisite control over both feature size and feature density. Here, we demonstrate a method for tracking atomically resolved and controlled structures from initial template definition through final nanostructure metrology, opening up a pathway for top-down atomic control over nanofabrication. Hydrogen depassivation lithography is the first step of the nanoscale fabrication process followed by selective atomic layer deposition of up to 2.8 nm of titania to make a nanoscale etch mask. Contrast with the background is shown, indicating different mechanisms for growth on the desired patterns and on the H passivated background. The patterns are then transferred into the bulk using reactive ion etching to form 20 nm tall nanostructures with linewidths down to ~6 nm. To illustrate the limitations of this process, arrays of holes and lines are fabricated. The various nanofabrication process steps are performed at disparate locations, so process integration is discussed. Related issues are discussed including using fiducial marks for finding nanostructures on a macroscopic sample and protecting the chemically reactive patterned Si(100)-H surface against degradation due to atmospheric exposure.

We report a protocol for combining the atomic metrology of the Scanning Tunneling Microscope for surface patterning with selective Atomic Layer Deposition and Reactive Ion Etching. Using a robust process involving numerous atmospheric exposures and transport, 3D nanostructures with atomic metrology are fabricated.

原子纳米结构可追溯制造

Reducing the scale of etched nanostructures below the 10 nm range eventually will require an atomic scale understanding of the entire fabrication process ...

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

低温碳纳米管垂直互连的制作兼容半导体技术

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

制备碳纳米管高频纳电子生物传感器的传感高离子强度的解决方案

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

生物工程

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

流动辅助介: 一种低成本的制备高性能溶液可纳米线器件的方法

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape method or individual WS2 nanotubes by dispersing the suspension of WS2 nanotubes. The selected samples have been fabricated into devices by the use of the electron beam lithography and electrolyte is put on the devices. We have characterized the electronic properties of the devices under applying the gate voltage. In the small gate voltage region, ions in the electrolyte are accumulated on the surface of the samples which leads to the large electric potential drop and resultant electrostatic carrier doping at the interface. Ambipolar transfer curve has been observed in this electrostatic doping region. When the gate voltage is further increased, we met another drastic increase of source-drain current which implies that ions are intercalated into layers of WS2 and electrochemical carrier doping is realized. In such electrochemical doping region, superconductivity has been observed. The focused technique provides a powerful strategy for achieving the electric-filed-induced quantum phase transition.

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

Here, we present a protocol to control the carrier number in solids by using the electrolyte.

用电解质浇注法对 WS2纳米器件电子态的电场控制

A method of carrier number control by electrolyte gating is demonstrated. We have obtained WS2 thin flakes with atomically flat surface via scotch tape ...